A leading-edge mobile application processor has over 11.8 billion transistors, 10 billion via connections and almost 16 layers of interconnects of varying dimensions, with those closest to the transistors being extremely narrow. As these tiny wires become narrower, the interconnect resistance increases exponentially – and higher resistance equates to higher power consumption. In fact, almost one-third of a chip's power is consumed by the interconnects; so in a sense, only a few atomic layers of materials are going to limit your cell phone's battery life. Luckily, Applied Materials is able to eliminate this critical roadblock to chip performance, power and scaling using a unique Integrated Materials Solution to carefully engineer the interfaces of the interconnect materials. This animation shows an Applied Materials Endura® system with many different technologies – ALD, PVD, CVD, interface engineering, surface treatment, reflow and on-board metrology – all integrated together in vacuum. Shown next to the system is a graphic depicting a magnified image of a copper via structure and the seven steps listed on the right show the process sequence happening inside the Endura system. It’s an incredible sequence of steps all done in vacuum to enable significantly lower interconnect resistance, which improves chip power consumption. And we are the only company that can achieve this as these Integrated Materials Solutions are unique and exclusive to Applied.

 24496      186